MSC8144EC Datasheet, PDF (59/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

2.7.11 ATM/UTOPIA/POS Timing
Table 52 provides the ATM/UTOPIA/POS input and output AC timing specifications.
Table 52. ATM/UTOPIA/POS AC Timing (External Clock) Specifications
Characteristic
Symbol
Min
Max
Unit
Outputs—External clock delay
t_UEKHOV
1
9
ns
Outputs—External clock High Impedance
t_UEKHOX
1
9
ns
Inputs—External clock input setup time
t_UEIVKH
4
ns
Inputs—External clock input hold time
t_UEIXKH
1
ns
Note:
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams also
apply when the falling edge is the active edge.
Figure 33 provides the AC test load for the ATM/UTOPIA/POS.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DD/2
Figure 33. ATM/UTOPIA/POS AC Test Load
Figure 34 shows the ATM/UTOPIA/UTOPIA timing with external clock.
CLK (input)
Input Signals:
t_UEIVKH
Output Signals:
t_UEIXKH
t_UEKHOV
t_UEKHOX
Figure 34. ATM/UTOPIAPOS AC Timing (External Clock)
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
59