MSC8144EC Datasheet, PDF (64/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Hardware Design Considerations
3 Hardware Design Considerations
The following sections discuss areas to consider when the MSC8144EC device is designed into a system.
3.1 Start-up Sequencing Recommendations
3.1.1 Power-on Sequence
Use the following guidelines for power-on sequencing:
• There are no dependencies in power-on/power-off sequence between V_DDM3 and V_DD supplies.
• There are no dependencies in power-on/power-off sequence between RapidIO supplies: V_DDSXC, V_DDSXP,
V_DDRIOPLL and other MSC8144EC supplies.
• V_DDPLL should be coupled with the V_DD power rail with extremely low impedance path.
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144EC device in the system during start-up. An assertion of the inputs to the high voltage level
before power-up should be with slew rate less than 4V/ns.
The following supplies should rise before any other supplies in any sequence
• V_DD and V_DDPLL coupled together
• V_DDM3
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 44):
• V_DDGE1
• V_DDGE2
• V_DDIO
• V_DDDDR and MV_REF coupled one to another. MV_REF should be either at same time or after V_DDDDR.
• V_DDM3IO
• V_25M3
I/O supplies
V_DDM3, V_DD, and V_DDPLL
90%
Figure 43. V_DDM3, V_DDM3IO and V_25M3 Power-on Sequence
Note:
1. This recommended power sequencing is different from the MSC8122/MSC8126.
2. If no pins that require V_DDGE1 as a reference supply are used (see Table 1), V_DDGE1 can be tied to GND.
3. If no pins that require V_DDGE2 as a reference supply are used (see Table 1), V_DDGE2 can be tied to GND.
4. If the DDR interface is not used, V_DDDDR and MV_REF can be tied to GND.
5. If the M3 memory is not used, V_DDM3, V_DDM3IO, and V_25M3 can be tied to GND.
6. If the RapidIO interface is not used, V_DDSX, V_DDSXP, and V_DDRIOPLL can be tied to GND.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
64
Freescale Semiconductor