MSC8144EC Datasheet, PDF (40/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
Table 28. DDR SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol ¹
Min
Max
Unit
MDQ/MECC/MDM output setup with respect to MDQS⁵
• 400 MHz
• 333 MHz
t_DDKHDS,
t_DDKLDS
700
900
—
ps
—
ps
• 266 MHz
1100
—
ps
• 200 MHz
1200
—
ps
MDQ/MECC/MDM output hold with respect to MDQS⁵
• 400 MHz
• 333 MHz
t_DDKHDX,
t_DDKLDX
700
900
—
ps
—
ps
• 266 MHz
1100
—
ps
• 200 MHz
1200
—
ps
MDQS preamble start⁶
MDQS epilogue end⁶
t_DDKHMP
–0.5 × t_MCK – 0.6 –0.5 × t_MCK +0.6
ns
t_DDKHME
–0.6
0.6
ns
Notes: 1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)} for
inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)} for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t_DDKHAS symbolizes DDR timing (DD) for the time t_MCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, t_DDKLDX symbolizes DDR timing (DD) for the time t_MCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by
1/2 applied cycle.
4. Note that t_DDKHMH follows the symbol conventions described in note 1. For example, t_DDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t_DDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t_DDKHMP follows the
symbol conventions described in note 1.
7. At recommended operating conditions with V_DDDDR (1.8 V or 2.5 V) ± 5%.
Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t_DDKHMH).
MCK[n]
MCK[n]
t_MCK
t_{DDKHMHmax) = 0.6 ns}
MDQS
t_{DDKHMH(min) = –0.6 ns}
MDQS
Figure 9. Timing for t_DDKHMH
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
40
Freescale Semiconductor