MSC8144EC Datasheet, PDF (48/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
V_DIFF max
V_DIFF min
0
–V_DIFF min
–V_DIFF max
0
A
B
1–B
1–A
1
Time (UI)
Figure 15. Receiver Input Compliance Mask
Table 40. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
1.25 GBaud
2.5 GBaud
3.125 GBaud
Receiver Type
V_DIFFmin (mV)
100
100
100
V_DIFFmax (mV)
800
800
800
A (UI)
0.275
0.275
0.275
B (UI)
0.400
0.400
0.400
2.7.5.7 Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.
802.3ae-2002™, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT
test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter
measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test
methods.
2.7.5.8 Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)
defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive
directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined
in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0.
The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10^–12. The eye pattern
shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of
the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω
resistive ±5% differential to 2.5 GHz.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
48
Freescale Semiconductor