MSC8144EC Datasheet, PDF (54/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

ETHMDC
ETHMDIO
(Input)
ETHMDIO
(Output)
t_MDC
t_MDCH
t_MDCR
t_MDHF
t_MDDVKH
t_MDDXKH
t_MDKHDX
Figure 25. MII Management Interface Timing
2.7.10.2 MII Transmit AC Timing Specifications
Table 46 provides the MII transmit AC timing specifications.
Table 46. MII Transmit AC Timing Specifications
Parameter/Condition
Symbol ¹
Min
Max
Unit
TX_CLK duty cycle
t_MTXH/t_MTX
35
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
t_MTKHDX
0
25
ns
TX_CLK data clock rise
t_MTXR
1.0
4.0
ns
TX_CLK data clock fall
t_MTXF
1.0
4.0
ns
Notes: 1. Typical TX_CLK period (t_MTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2. Program GCR4 as 0x00030CC3.
Figure 26 shows the MII transmit AC timing diagram.
TX_CLK
TXD[3:0]
TX_EN
TX_ER
t_MTX
t_MTXR
t_MTXH
t_MTXF
t_MTKHDX
Figure 26. MII Transmit AC Timing
2.7.10.3 MII Receive AC Timing Specifications
Table 47 provides the MII receive AC timing specifications.
RX_CLK duty cycle
Table 47. MII Receive AC Timing Specifications
Parameter/Condition
Symbol ¹
Min
t_MRXH/t_MRX
35
Max
65
Unit
%
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
54
Freescale Semiconductor