MSC8144EC Datasheet, PDF (60/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

2.7.12 SPI Timing
Table 52 provides the SPI input and output AC timing specifications.
Table 53. SPI AC Timing Specifications ¹
Characteristic
Symbol ²
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
t_NIKHOV
6
ns
SPI outputs hold—Master mode (internal clock) delay
t_NIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
t_NEKHOV
8
ns
SPI outputs hold—Slave mode (external clock) delay
t_NEKHOX
2
ns
SPI inputs—Master mode (internal clock input setup time
t_NIIVKH
4
ns
SPI inputs—Master mode (internal clock input hold time
t_NIIXKH
0
ns
SPI inputs—Slave mode (external clock) input setup time
t_NEIVKH
4
ns
SPI inputs—Slave mode (external clock) input hold time
t_NEIXKH
2
ns
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)} for inputs
and t_{(first two letters of functional block)(reference)(state)(signal)(state)} for outputs. For example, t_NIKHOX symbolizes the internal timing
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 35 provides the AC test load for the SPI.
Output
Z₀ = 50 Ω
R_L = 50 Ω
OV_DD/2
Figure 35. SPI AC Test Load
Figure 36 through Figure 37 represent the AC timings from Table 52. Note that although the specifications generally reference
the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 36 shows the SPI timings in slave mode (external clock).
SPICLK (Input)
Input Signals:
SPIMOSI
(See Note)
t_NEIVKH
t_NEIXKH
Output Signals:
SPIMISO
(See Note)
t_NEKHOX
Note: The clock edge is selectable on SPI.
Figure 36. SPI AC Timing in Slave Mode (External Clock)
Figure 37 shows the SPI timings in master mode (internal clock).
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
60
Freescale Semiconductor