MSC8144EC Datasheet, PDF (61/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

SPICLK (Output)
Input Signals:
SPIMISO
(See Note)
t_NIIVKH
t_NIIXKH
Output Signals:
SPIMOSI
(See Note)
t_NIKHOX
Note: The clock edge is selectable on SPI.
Figure 37. SPI AC Timing in Master Mode (Internal Clock)
2.7.13 Asynchronous Signal Timing
Table 54. Signal Timing
Input
Output
Note:
Characteristics
Symbol
t_IN
t_OUT
1. Relevant for EE0, IRQ[15–0], and NMI only.
Type
Asynchronous
Asynchronous
Min
One CLKIN cycle¹
Application dependent
The following interfaces use the specified asynchronous signals:
• GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are
not selected.
Note:
•
•
•
•
•
When used as a GPI, the input should be driven until it is acknowledged by the device; the GPIO input status is read
from a register.
EE port. Signals EE0, EE1, EE2_0, EE2_1, EE2_2, and EE2_3.
Boot function. Signal STOP_BS.
I²C interface. Signals I2C_SCL and I2C_SDA.
Interrupt inputs. Signals IRQ[15–0] and NMI.
Interrupt outputs. Signals INT_OUT and NMI_OUT (pulse width is 10 ns).
Figure 38 shows the behavior of the asynchronous signals.
t_IN
Input
Output
t_OUT
Figure 38. Asynchronous Signal Timing
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
61