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LM3S610_06 Datasheet, PDF (98/396 Pages) List of Unclassifed Manufacturers – Microcontroller
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Internal Memory
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134
Note: Offset is relative to System Control base address of 0x400FE000
These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each
2 KB flash block. This register is loaded during the power-on reset sequence.
The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. However, this register is R/W0; the user can only
change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 94.
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Offset 0x130 and 0x134
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
Block15 Block14
RR/WO 0
01
RR/WO 0
01
Block13
RR/WO 0
01
Blockre1s2erveBdlock11 Block10
RR/WO 0
01
RR/WO 0
01
RR/WO 0
01
Block9
RR/WO 0
01
Block8
RR/WO 0
01
Block7
R/W0
1
Block6
R/W0
1
Block5
R/W0
1
Block4
R/W0
1
Block3
R/W0
1
Block2
R/W0
1
Block1
R/W0
1
Block0
R/W0
1
Bit/Field
31:16
15:0
Name
reserved
Block15-
Block0
Type
RO
R/W0
Reset
0
1
Description
Reserved bits return an indeterminate value, and
should never be changed.
Enable 2 KB flash blocks to be written or erased
(FMPPE register), or executed or read (FMPRE
register). The policies may be combined as shown
in Table 7-1 on page 95.
98
October 8, 2006
Preliminary
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