LM3S610_06 Datasheet, PDF (310/396 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
14.3
Table 14-1 gives examples of Timer period, system clock, and speed mode (Standard or Fast).
Table 14-1. Examples of I²C Master Timer Period versus Speed Mode
System
Clock
4 Mhz
6 Mhz
12.5 Mhz
16.7 Mhz
20 Mhz
25 Mhz
33Mhz
40Mhz
50Mhz
Timer
Period
0x01
0x02
0x06
0x08
0x09
0x0C
0x10
0x13
0x18
Standard
Mode
100 Kbps
100 Kbps
89 Kbps
93 Kbps
100 Kbps
96.2 Kbps
97.1 Kbps
100 Kbps
100 Kbps
Timer
Period
-
-
0x01
0x02
0x02
0x03
0x04
0x04
0x06
Fast
Mode
-
-
312 Kbps
278 Kbps
333 Kbps
312 Kbps
330 Kbps
400 Kbps
357 Kbps
Initialization and Configuration
The following example shows how to configure the I²C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I²C clock by writing a value of 0x00001000 to the RCGC1 register in the System
Control module.
2. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
3. Initialize the I²C Master by writing the I2CMCR register with a value of 0x00000020.
4. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock
periods in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x00000009.
5. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x00000076. This sets the slave address to 0x3B.
6. Place data (byte) to be sent in the data register by writing the I2CMDR register with the
desired data.
7. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x00000007 (STOP, START, RUN).
8. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
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October 8, 2006
Preliminary