LM3S610_06 Datasheet, PDF (11/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
List of Registers
System Control ............................................................................................................................... 51
Register 1: Device Identification 0 (DID0), offset 0x000 .............................................................................. 59
Register 2: Device Identification 1 (DID1), offset 0x004 .............................................................................. 60
Register 3: Device Capabilities 0 (DC0), offset 0x008................................................................................. 62
Register 4: Device Capabilities 1 (DC1), offset 0x010................................................................................. 63
Register 5: Device Capabilities 2 (DC2), offset 0x014................................................................................. 65
Register 6: Device Capabilities 3 (DC3), offset 0x018................................................................................. 66
Register 7: Device Capabilities 4 (DC4), offset 0x01C ................................................................................ 68
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................ 69
Register 9: LDO Power Control (LDOPCTL), offset 0x034.......................................................................... 70
Register 10: Software Reset Control 0 (SRCR0), offset 0x040 ..................................................................... 71
Register 11: Software Reset Control 1 (SRCR1), offset 0x044 ..................................................................... 72
Register 12: Software Reset Control 2 (SRCR2), offset 0x048 ..................................................................... 73
Register 13: Raw Interrupt Status (RIS), offset 0x050................................................................................... 74
Register 14: Interrupt Mask Control (IMC), offset 0x054 ............................................................................... 75
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058.......................................................... 77
Register 16: Reset Cause (RESC), offset 0x05C .......................................................................................... 78
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060................................................................. 79
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064 .................................................................... 84
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 ....................................................... 85
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110..................................................... 85
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120........................................... 85
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 ....................................................... 87
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114..................................................... 87
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124........................................... 87
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 ....................................................... 89
Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118..................................................... 89
Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128........................................... 89
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .............................................. 90
Register 29: Clock Verification Clear (CLKVCLR), offset 0x150.................................................................... 91
Register 30: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ....................................... 92
Internal Memory .............................................................................................................................. 93
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ............................................... 98
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .......................................... 98
Register 3: USec Reload (USECRL), offset 0x140...................................................................................... 99
Register 4: Flash Memory Address (FMA), offset 0x000 ........................................................................... 100
Register 5: Flash Memory Data (FMD), offset 0x004 ................................................................................ 101
Register 6: Flash Memory Control (FMC), offset 0x008 ............................................................................ 102
Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................. 104
Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 ............................................................. 105
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014......................... 106
General-Purpose Input/Outputs (GPIOs) .................................................................................... 107
Register 1: GPIO Data (GPIODATA), offset 0x000 ................................................................................... 115
Register 2: GPIO Direction (GPIODIR), offset 0x400 ................................................................................ 116
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404......................................................................... 117
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408.............................................................. 118
October 8, 2006
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Preliminary