LM3S610_06 Datasheet, PDF (207/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INR3 INR2 INR1 INR0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
INR3
2
INR2
1
INR1
0
INR0
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Set by hardware when a sample with its respective
ADCSSCTL3 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN3 bit.
Set by hardware when a sample with its respective
ADCSSCTL2 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN2 bit.
Set by hardware when a sample with its respective
ADCSSCTL1 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN1 bit.
Set by hardware when a sample with its respective
ADCSSCTL0 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN0 bit.
October 8, 2006
207
Preliminary