LM3S610_06 Datasheet, PDF (204/396 Pages) List of Unclassifed Manufacturers – Microcontroller

Analog-to-Digital Converter (ADC)
11.4
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the
corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure
that the END bit is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
Register Map
Table 11-2 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the ADC base address of 0x40038000.
Table 11-2. ADC Register Map
Offset Name
Reset
Type Description
See
page
0x000 ADCACTSS
0x00000000 R/W Active sample sequencer
206
0x004 ADCRIS
0x00000000 RO Raw interrupt status and clear
207
0x008 ADCIM
0x00000000 R/W Interrupt mask
208
0x00C ADCISC
0x00000000 R/W1C Interrupt status and clear
209
0x010 ADCOSTAT
0x00000000 R/W1C Overflow status
210
0x014 ADCEMUX
0x00000000 R/W Event multiplexer select
211
0x018 ADCUSTAT
0x00000000 R/W1C Underflow status
212
0x020 ADCSSPRI
0x00003210 R/W Sample sequencer priority
213
0x028 ADCPSSI
-
WO Processor sample sequence initiate
214
0x030 ADCSAC
0x00000000 R/W Sample averaging control
215
0x040 ADCSSMUX0
0x00000000 R/W Sample sequence input multiplexer select 0
216
0x044 ADCSSCTL0
0x00000000 R/W Sample sequence control 0
218
0x048 ADCSSFIFO0
0x00000000 RO Sample sequence result FIFO 0
220
0x04C ADCSSFSTAT0 0x00000100 RO Sample sequence FIFO 0 status
221
0x060 ADCSSMUX1
0x00000000 R/W Sample sequence input multiplexer select 1
222
0x064 ADCSSCTL1
0x00000000 R/W Sample sequence control 1
223
0x068 ADCSSFIFO1
0x00000000 RO Sample sequence result FIFO 1
223
0x06C ADCSSFSTAT1 0x00000100 RO Sample sequence FIFO 1 status
223
0x080 ADCSSMUX2
0x00000000 R/W Sample sequence input multiplexer select 2
224
0x084 ADCSSCTL2
0x00000000 R/W Sample sequence control 2
225
0x088 ADCSSFIFO2
0x00000000 RO Sample sequence result FIFO 2
225
204
October 8, 2006
Preliminary