LM3S610_06 Datasheet, PDF (287/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
Offset 0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXMIS RXMIS RTMIS RORMIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
TXMIS
2
RXMIS
1
RTMIS
0
RORMIS
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
October 8, 2006
287
Preliminary