LM3S610_06 Datasheet, PDF (303/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
14.2.1.4
Byte Format
Every byte put out on the SDA line must be 8-bits long. The number of bytes per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the
MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL
Low and force the transmitter into a wait state. The data transfer continues when the receiver
releases the clock SCL.
14.2.1.5
Acknowledge
Data transfer with an acknowledge is obligatory. The acknowledge-related clock pulse is
generated by the master. The transmitter releases the SDA line during the acknowledge clock
pulse.
The receiver must pull down SDA during the acknowledge clock pulse such that it remains stable
(Low) during the High period of the acknowledge clock pulse.
When a slave receiver does not acknowledge the slave address, the data line must be left in a
High state by the slave. The master can then generate a STOP condition to abort the current
transfer.
If the master receiver is involved in the transfer, it must signal the end of data to the
slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the
slave. The slave-transmitter must release the SDA line to allow the master to generate the STOP
or a repeated START condition.
14.2.1.6
Arbitration
A master may start a transfer only if the bus is idle. Two or more masters may generate a START
condition within minimum hold time of the START condition. Arbitration takes place on the SDA
line, while SCL is in the High state, in such a manner that the master transmitting a High level
(while another master is transmitting a Low level) will switch off its data output stage.
Arbitration can be over several bits. Its first stage is a comparison of address bits. If both masters
are trying to address the same device, arbitration continues with comparison of data bits.
14.2.1.7
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 14-5. After the START condition, a slave address
is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in
the I2CMSA register). A zero indicates a transmission (Send); a one indicates a request for data
(Receive). A data transfer is always terminated by a STOP condition generated by the master.
However, a master can still communicate on the bus by generating a repeated START condition
and addressing another slave without first generating a STOP condition. Various combinations of
receive/send formats are then possible within such a transfer.
Figure 14-5. Complete Data Transfer with a 7-Bit Address
SDA
MSB
LSB
R/S
ACK
MSB
LSB
ACK
SCL
1
2
7
8
9
Slave address
1
2
7
8
9
Data
The first seven bits of the first byte make up the slave address (see Figure 14-6). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
master will write (send) information to a selected slave. A one in this position means that the
master will receive information from the slave.
October 8, 2006
303
Preliminary