LM3S610_06 Datasheet, PDF (267/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
13.2
13.2.1
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered
with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both
transmit and receive modes.
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 284). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see
page 278).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
13.2.2
13.2.2.1
13.2.2.2
13.2.3
Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For transmit operations, the system clock must be at least two times
faster than the SSIClk. For receive operations, the system clock must be at least 12 times faster
than the SSIClk.
See “Electrical Characteristics” on page 377 to view SSI timing parameters.
FIFO Operation
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 282), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to
serial conversion and transmission to the attached slave or master, respectively, through the
SSITx pin.
Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
Interrupts
The SSI can generate interrupts when the following conditions are observed:
„ Transmit FIFO service
„ Receive FIFO service
„ Receive FIFO time-out
„ Receive FIFO overrun
October 8, 2006
267
Preliminary