LM3S610_06 Datasheet, PDF (86/396 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
11:8
Name
MAXADCSPD
Type
R/W
Reset
0x2
Description
This field sets the rate at which the ADC samples data. A
value of 0x2 indicates the maximum rate of 500K samples
per second. You cannot set the rate higher than the
maximum rate.
You can set the sample rate by setting the MAXADCSPD bit
as follows:
Value
0x0
0x1
0x2
Sample Rate
125K samples/second
250K samples/second
500K samples/second
7:4
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
3
WDT
R/W
0
This bit controls the clock gating for the WDT module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
2
SWO
R/W
0
This bit controls the clock gating for the SWO module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
1
SWD
R/W
0
This bit controls the clock gating for the SWD module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
0
JTAG
R/W
1
This bit controls the clock gating for the JTAG module.
The reset state for this bit is 1. At reset, the unit receives a
clock and functions. Setting this bit to 0 leaves the unit
unclocked and disabled.^a
a. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
86
October 8, 2006
Preliminary