LM3S610_06 Datasheet, PDF (201/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
11.2
11.2.1
Functional Description
The Stellaris ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing
the ADC to collect data from multiple input sources without having to be re-configured or serviced
by the controller. The programming of each sample in the sample sequence includes parameters
such as the input source and mode (differential versus single-ended input), interrupt generation on
sample completion, and the indicator for the last sample in the sequence.
Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the
sequencers are identical in implementation except for the number of samples that can be captured
and the depth of the FIFO. Table 11-1 shows the maximum number of samples that each
Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry
is a 32-bit word, with the lower 10 bits containing the conversion result.
Table 11-1. Samples and FIFO Depth of Sequencers
Sequencer
Number of
Samples
Depth of FIFO
SS3
1
1
SS2
4
4
SS1
4
4
SS0
8
8
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample Sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same
sequence is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set
for any combination of samples, allowing interrupts to be generated after every sample in the
sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For
example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth
sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth
sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status
(ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow
conditions are monitored using the ADCOSTAT and ADCUSTAT registers.
October 8, 2006
201
Preliminary