LM3S610_06 Datasheet, PDF (13/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Control (WDTCTL), offset 0x008............................................................................ 182
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 183
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 184
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 185
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 186
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 187
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 188
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 189
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 190
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 191
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 192
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 193
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 194
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 195
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 196
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 197
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 198
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 199
Analog-to-Digital Converter (ADC).............................................................................................. 200
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .................................................. 206
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004................................................................. 207
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ............................................................................ 208
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C........................................................ 209
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 .................................................................. 210
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ...................................................... 211
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ................................................................ 212
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020.................................................. 213
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ..................................... 214
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ...................................................... 215
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040.................. 216
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044............................................. 218
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048.................................... 220
Register 14: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C................................ 221
Register 15: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060.................. 222
Register 16: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064............................................. 223
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068.................................... 223
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C................................ 223
Register 19: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080.................. 224
Register 20: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084............................................. 225
Register 21: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088.................................... 225
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C................................ 225
Register 23: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ................. 226
Register 24: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x064............................................. 227
Register 25: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ................................... 227
Register 26: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................... 227
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ............................................................ 228
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 230
Register 1: UART Data (UARTDR), offset 0x000 ...................................................................................... 237
October 8, 2006
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Preliminary