LM3S610_06 Datasheet, PDF (320/396 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
Offset 0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
16
RO
RO
0
0
1
0
IM
RO
R/W
0
0
Bit/Field
31:1
0
Name
reserved
IM
Type
RO
R/W
Reset
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls whether a raw interrupt is promoted to a
controller interrupt. If set, the interrupt is not masked and
the interrupt is promoted; otherwise, the interrupt is
masked.
320
October 8, 2006
Preliminary