LM3S610_06 Datasheet, PDF (347/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection; it
must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see
page 348). The PWM generator interrupts simply reflect the status of the PWM generators; they
are cleared via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the
events that are active; a zero bit indicates that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Offset 0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
IntFault
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntPWM2 IntPWM1 IntPWM0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
15:3
2
1
0
Name
reserved
IntFault
reserved
IntPWM2
IntPWM1
IntPWM0
Type
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that the fault input has been asserted.
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that the PWM generator 2 block is asserting its
interrupt.
Indicates that the PWM generator 1 block is asserting its
interrupt.
Indicates that the PWM generator 0 block is asserting its
interrupt.
October 8, 2006
347
Preliminary