LM3S610_06 Datasheet, PDF (9/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Figure 14-10. Master Burst RECEIVE ........................................................................................................... 307
Figure 14-11. Master Burst RECEIVE after Burst SEND............................................................................... 308
Figure 14-12. Master Burst SEND after Burst RECEIVE............................................................................... 308
Figure 14-13. Slave Command Sequence..................................................................................................... 309
Figure 15-1. PWM Module Block Diagram................................................................................................... 333
Figure 15-2. PWM Count-Down Mode......................................................................................................... 334
Figure 15-3. PWM Count-Up/Down Mode ................................................................................................... 335
Figure 15-4. PWM Generation Example In Count-Up/Down Mode ............................................................. 335
Figure 15-5. PWM Dead-Band Generator ................................................................................................... 336
Figure 16-1. Pin Connection Diagram.......................................................................................................... 366
Figure 19-1. Load Conditions....................................................................................................................... 380
Figure 19-2. I²C Timing................................................................................................................................ 382
Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 383
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 384
Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 384
Figure 19-6. JTAG Test Clock Input Timing................................................................................................. 386
Figure 19-7. JTAG Test Access Port (TAP) Timing ..................................................................................... 386
Figure 19-8. JTAG TRST Timing ................................................................................................................. 386
Figure 19-9. External Reset Timing (RST)................................................................................................... 388
Figure 19-10. Power-On Reset Timing .......................................................................................................... 388
Figure 19-11. Brown-Out Reset Timing ......................................................................................................... 388
Figure 19-12. Software Reset Timing ............................................................................................................ 388
Figure 19-13. Watchdog Reset Timing .......................................................................................................... 389
Figure 19-14. LDO Reset Timing ................................................................................................................... 389
Figure 20-1. 48-Pin LQFP Package............................................................................................................. 390
October 8, 2006
9
Preliminary