LM3S610_06 Datasheet, PDF (331/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
Offset 0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
16
RO
RO
0
0
1
0
MIS
RO
RO
0
0
Bit/Field
31:1
0
Name
reserved
MIS
Type
RO
RO
Reset
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies the raw interrupt state (after masking) of
the I²C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit
was last cleared.
October 8, 2006
331
Preliminary