LM3S610_06 Datasheet, PDF (77/396 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 74).
Masked Interrupt Status and Clear (MISC)
Offset 0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PLLLMIS CLMIS IOFMIS MOFMIS LDOMIS BORMIS PLLFMIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C R/W1C
R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:7
6
Name
reserved
PLLLMIS
Type
RO
R/W1C
5
CLMIS
R/W1C
4
IOFMIS
R/W1C
3
MOFMIS
R/W1C
2
LDOMIS
R/W1C
1
BORMIS
R/W1C
0
PLLFMIS
R/W1C
Reset
0
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
PLL Lock Masked Interrupt Status
This bit is set when the PLL T_READY timer asserts. The
interrupt is cleared by writing a 1 to this bit.
Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt
is cleared by writing a 1 to this bit.
Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
LDO Power Unregulated Masked Interrupt Status
This bit is set if LDO power is unregulated. The interrupt is
cleared by writing a 1 to this bit.
Brown-Out Reset Masked Interrupt Status
This bit is the masked interrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in the PBORCTL register is cleared.
The interrupt is cleared by writing a 1 to this bit.
PLL Fault Masked Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
The interrupt is cleared by writing a 1 to this bit.
October 8, 2006
77
Preliminary