LM3S610_06 Datasheet, PDF (309/396 Pages) List of Unclassifed Manufacturers – Microcontroller

Figure 14-13. Slave Command Sequence
Idle
write OWN Slave
address to I2CSOAR
write “-------1”
to I2CSCSR
read I2CSCSR
N ^{RREQ=”1” Y}
read Data from
I2CSDR
N ^{TREQ=”1” Y}
write Data to
I2CSDR
LM3S610 Data Sheet
14.2.2
Available Speed Modes
The SCL clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and
SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the Low phase of the SCL clock (fixed at 6)
SCL_HP is the High phase of the SCL clock (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 319).
The SCL clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
October 8, 2006
309
Preliminary