LM3S610_06 Datasheet, PDF (14/396 Pages) List of Unclassifed Manufacturers – Microcontroller

List of Registers
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 239
UART Flag (UARTFR), offset 0x018 ....................................................................................... 241
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 243
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 244
UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 245
UART Control (UARTCTL), offset 0x030................................................................................. 247
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 248
UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 249
UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 251
UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 252
UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 253
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 254
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 255
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 256
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 257
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 258
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 259
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 260
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 261
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 262
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 263
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 264
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 265
Synchronous Serial Interface (SSI) ............................................................................................. 266
Register 1: SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 278
Register 2: SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 280
Register 3: SSI Data (SSIDR), offset 0x008 .............................................................................................. 282
Register 4: SSI Status (SSISR), offset 0x00C ........................................................................................... 283
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 284
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 285
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 286
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 287
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 288
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 289
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 290
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 291
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 292
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 293
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 294
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 295
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 296
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 297
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 298
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 299
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 300
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 301
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ................................................................ 312
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004................................................................. 313
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October 8, 2006
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