AK4671_10 Datasheet, PDF (94/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
<Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2)
P M L O 3 b it
P M R O 3 b it
(1)
(3)
L O P S 3 b it
(5)
(4 )
(6)
L O U T 3 , R O U T 3 p in s
≥ 300 ms
N orm al O utput
≥ 300 m s
Figure 76. Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO3=PMRO3 bits = “1”. Stereo line output exits the power-down mode.
LOUT3 and ROUT3 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS3 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO3=PMRO3 bits = “0”. Stereo line output enters power-down mode.
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins fall down. Stereo line output exits the power-save mode.
MS0666-E-02
- 94 -
2010/06