AK4671_10 Datasheet, PDF (101/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
a) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via
SYNCB and BICKB pins.
AK4671
Phone Module
SYNCA
BICKA
SDTOA
SDTIA
1fs2
≥ 16fs2
SYNC
BICK
SDTI
SDTO
SYNCB
BICKB
SDTOB
SDTIB
1fs2
16fs2 or 32fs2
Bluetooth Module
SYNC
BICK
SDTI
SDTO
Figure 82. PCM I/F (PLLBT Reference Clock: SYNCA or BICKA pin)
b) PLLBT reference clock: SYNCB or BICKB pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via
SYNCA and BICKA pins.
AK4671
Phone Module
SYNCA
BICKA
SDTOA
SDTIA
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTI
SDTO
SYNCB
BICKB
SDTOB
SDTIB
1fs2
≥ 16fs2
Bluetooth Module
SYNC
BICK
SDTI
SDTO
Figure 83. PCM I/F (PLLBT Reference Clock: SYNCB or BICKB pin)
PLLBT should always be powered-up (PMPCM bit = “1”) whenever SRC-A or SRC-B is in operation (PMSRA bit = “1”
or PMSRB bit = “1”). If PLLBT is powered-down, the AK4671 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If PLLBT is powered-down, SRC-A, SRC-B and SRC-C
should be in the power-down mode (PMSRA=PMSRB bits = “0”).
MS0666-E-02
- 101 -
2010/06