AK4671_10 Datasheet, PDF (44/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4671 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not
available.
1) Setting of PLL Mode
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
Mode
bit
bit
bit
bit Clock Input Pin Frequency
R and C of
VCOC pin
R[Ω] C[F]
0
0
0
0
0
LRCK pin
1fs
6.8k 220n
2
0
0
1
0
BICK pin
32fs
10k 4.7n
10k 10n
3
0
0
1
1
BICK pin
64fs
10k 4.7n
10k 10n
4
0
1
0
0
MCKI pin 11.2896MHz 10k 4.7n
5
0
1
0
1
MCKI pin
12.288MHz 10k 4.7n
6
0
1
1
0
MCKI pin
12MHz
10k 10n
7
0
1
1
1
MCKI pin
24MHz
10k 10n
8
1
0
0
0
MCKI pin
19.2MHz 10k 4.7n
12
1
1
0
0
MCKI pin
13.5MHz 10k 10n
13
1
1
0
1
MCKI pin
27MHz
10k 10n
14
1
1
1
0
MCKI pin
13MHz
10k 220n
15
1
1
1
1
MCKI pin
26MHz
10k 220n
Others
Others
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
PLL Lock
Time
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
5
0
1
0
1
11.025kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
15
1
1
1
1
44.1kHz
(default)
Others
Others
N/A
(N/A: Not available)
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0666-E-02
- 44 -
2010/06