AK4671_10 Datasheet, PDF (116/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4671. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 7-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 5AH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK4671 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ (except for 10bit SAR ADC Data)
The AK4671 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4671 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4671
ceases transmission.
S
T
A
R/W="1"
R
T
SDA
Slave
S _Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
A
MA
MA
MA MA
C
AC
AC
AC
AC
K
S
T
K
S
T
K
S
T
K
S
T
K
E
E
E
E
R
R
R
R
Figure 102. CURRENT ADDRESS READ
S
T
O
P
P
MN
AA
S
T
E
C
K
R
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4671 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4671 ceases transmission.
S
T
A
R/W ="0"
R
T
S
T
A
R/W ="1"
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
Data(n+x)
A
A
A
MA
MA MA
C
C
C
AC
AC
AC
K
K
K
S
T
K
S
T
K
S
T
K
E
E
E
R
R
R
Figure 103. RANDOM ADDRESS READ (Except for 10bit SAR ADC Data)
S
T
O
P
P
MN
AA
S
T
C
EK
R
When SAR ADC data is read, 5BH should be set as register address and 2 byte data should be read by RANDOM
ADDRESS READ, then stop condition should be input. A/D readout format is MSB first, 2 byte width. Upper 10bits are
valid on 2byte (16-bit), and lower 6bits are filled with zero.
S
S
T
T
S
A
R/W ="0"
A
R/W ="1"
T
R
R
O
T
T
P
SDA
Slave
S _Address
Sub
Address(5BH)
Slave
S _Address
Data(D9-2)
Data(D1-0)
P
A
A
A
MA
MN
C
C
C
AC
AA
K
K
K
S
T
K
E
S
T
E
C
K
R
R
Figure 104. RANDOM ADDRESS READ (10bit SAR ADC Data)
MS0666-E-02
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2010/06