AK4671_10 Datasheet, PDF (51/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ System Reset
When power-up, the AK4671 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAL
and PMDAR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
ADC digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input
signal after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an
initialization cycle.
■ Audio Interface Format
Four types of data formats are available and can be selected by setting the DIF1-0 bits (Table 16). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC) SDTI (DAC)
DSP Mode
DSP Mode
MSB justified LSB justified
MSB justified
I²S compatible
MSB justified
I²S compatible
Table 16. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Table 17
Figure 49
Figure 50
Figure 51
(default)
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 17).
DIF1
0
DIF0
0
MSBS
0
0
1
1
BCKP
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the
0
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
1
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
0 (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
1 (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
Table 17. Audio Interface Format in Mode 0
Figure
Figure 45
Figure 46
Figure 47
Figure 48
(default)
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0666-E-02
- 51 -
2010/06