AK4671_10 Datasheet, PDF (84/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
<Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2)
P M L O 1 b it
P M R O 1 b it
(1)
(3)
L O P S 1 b it
(5)
(4 )
(6)
L O U T 1 p in
R O U T 1 p in
≥ 300 ms
N orm al O utput
≥ 300 m s
Figure 66. Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS1 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO1=PMRO1 bits = “1”. Stereo line output exits the power-down mode.
LOUT1 and ROUT1 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS1 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO1=PMRO1 bits = “0”. Stereo line output enters power-down mode.
LOUT1 and ROUT1 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins fall down. Stereo line output exits the power-save mode.
MS0666-E-02
- 84 -
2010/06