AK4671_10 Datasheet, PDF (114/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ Serial Control Interface
(1) 4-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO).
In case except for 10bit SAR ADC data read, the data on this interface consists of a 3-bit Chip address (fixed to “100”),
Read/Write (1bit), Register address (MSB first, 7bits) and Control data (MSB first, 8bits).
In case of 10bit SAR ADC data read, the data on this interface consists of a 3-bit Chip address (fixed to “101”),
Read/Write (1bit: fixed to “0”) and SAR ADC Data (MSB first, 10bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Address and data
are latched on the 24th CCLK rising edge (“↑”) after CSN falling edge (“↓”) for write operations and CDTO bit goes to
Hi-Z after CSN rising edge (“↑”). CSN should be set to “H” once after 24th CCLK for each address. The clock speed of
CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CCLK
Clock,
"H" or "L"
Clock,
"H" or "L"
"H" or "L"
"H" or "L"
CDTI
WRITE
C2 C1 R/W C0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CDTO
Hi-Z
READ
(except for
10bit SAR ADC Data)
"H" or "L"
"H" or "L"
CDTI
C2 C1 R/W C0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CDTO
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C2-C0: Chip Address (Fixed to “100”)
R/W: READ/WRITE (0: READ, 1: WRITE)
A6-A0: Register Address
D7-D0: Control Data
Figure 96. Serial Control I/F Timing (Except for 10bit SAR ADC Data)
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CCLK
Clock,
"H" or "L"
Clock,
"H" or "L"
"H" or "L"
"H" or "L"
READ
(10bit SAR ADC Data)
CDTI
CDTO
C2 C1 R/W C0 0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0
C2-C0: Chip Address (Fixed to “101”)
R/W: READ/WRITE (Fixed to “0”: READ Only)
D9-D0: SAR ADC Data
Figure 97. Serial Control I/F Timing (10bit SAR ADC Data)
MS0666-E-02
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2010/06