AK4671_10 Datasheet, PDF (102/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ PCM I/F Master Mode/Slave Mode
The PLLBT2 bit selects either master or slave mode (Table 80). When either PCM I/F A or PCM I/F B is set in slave
mode, the other is set in master mode. (For example, when PCM I/F B is set in slave mode, PCM I/F A is set in master
mode.) When the AK4671 is power-down mode (PDN pin = “L”) or PMPCM bit = “0”, each clock pins (SYNCA,
BICKA, SYNCB, BICKB) of PCM I/F become a Hi-Z (Table 81).
PLLBT3-0 bits should be set when PMPCM bit = “0” to avoid shorting out of the slave mode clock pins and master mode
clock output.
After setting the PDN pin = “H”, the PCM I/F clock pins are the Hi-Z state until PMPCM bit becomes “1”. The PCM I/F
clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
PLLBT2 bit
0
1
PCM I/F A
Slave Mode
Master Mode
SYNCA, BICKA pins
PCM I/F B
SYNCB, BICKB pins
Input
Master Mode
Output
Output
Slave Mode
Input
Table 80. Select PCM I/F Master/Slave Mode
(default)
PDN pin
L
H
PMPCM bit SYNCA, BICKA pin
SYNCB, BICKB pin
-
Hi-Z
Hi-Z
0
Hi-Z
Hi-Z
1
I/O Select by PLLBT2 bit I/O Select by PLLBT2 bit
(Table 80)
(Table 80)
Table 81. PCM I/F Clock I/O State
MS0666-E-02
- 102 -
2010/06