AK4671_10 Datasheet, PDF (135/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
Addr
17H
Register Name
ALC Mode Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH1 LMTH0
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 24)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (Table 28)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 25)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
Addr
18H
Register Name
Mode Control 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DAM MIXD SDIM1 SDIM0
EQ
ADM IVOLC ALC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
0
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
ADM: Mono Recording (Table 44)
0: Stereo (default)
1: Mono: (L+R)/2
EQ: Select 5-Band Equalizer
0: OFF (default)
1: ON
SDIM1-0: SDTI Input Signal Select (Table 48)
Default: “00” (L=Lch, R=Rch)
MIXD: DAC and SRC-A Mono Mixing (Table 53 and Table 54)
0: L+R (default)
1: (L+R)/2
DAM: DAC Mono Mixing (Table 53)
0: Stereo (default)
1: Mono: (L+R) or (L+R)/2 is selected by MIXD bit.
MS0666-E-02
- 135 -
2010/06