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AK4671_10 Datasheet, PDF (154/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP | |||
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[AK4671]
â Stereo Line Output
FS3-0 bits
(Addr:01H, D7-4)
0000
(1)
L3VL1-0 bits
10
(Addr:11H, D7-D6)
(2)
PFSEL bis
(Addr:1DH, D0)
PFMXL/R1-0 bits 0000
(Addr:15H, D3-0)
DACSL/R bits
(Addr:0DH&0EH, D0)
1111
01
0101
(9)
OVL/R7-0 bits 18H
(Addr:1AH&1BH, D7-0)
LOPS3 bit
(Addr:11H, D2)
PMDAL/R bits
(Addr:00H, D7-6)
PML/RO3 bits
(Addr:11H, D1-0)
LOUT3 pin
ROUT3 pin
28H
(3)
(4)
(6)
(7)
(10)
(5)
>300 ms
Normal Output
(8)
>300 ms
Example:
PLL, Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
OVOLC bit = â1â(default)
Digital Volume Level: â8dB
LINEOUT Volume Level: â3dB
(1) Addr:01H, Data:F4H
(2) Addr:11H, Data:40H
Addr:1DH, Data:01H
Addr:15H, Data:05H
Addr:0DH&0EH, Data:01H
(3) Addr:1AH&1BH, Data:28H
(4) Addr:11H, Data:44H
(5) Addr:00H, Data:C1H
Addr:11H, Data:47H
(6) Addr:11H, Data:43H
Playback
(7) Addr:11H, Data:47H
(8) Addr:00H, Data:01H
Addr:11H, Data:44H
(9) Addr:0DH&0E, Data:00H
(10) Addr:11H, Data:40H
Figure 116. Stereo Lineout Sequence
(Speaker Playback: SDTI â Audio I/F â SVOLA â DATT â DACL/R â LOUT3/ROUT3 â External SPK-Amp)
<Example>
At first, clocks should be supplied according to âClock Set Upâ sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of âSDTI Ã DAC Ã Stereo Line-Ampâ: PFSEL = â0â Ã â1â, PFMXL1-0 = PFMXR1-0 bits =
â0000â Ã â0101â, DACSL = DACSR bits = â0â Ã â1â
Set up analog volume for Stereo Line-Amp (Addr: 11H, L3VL1-0 bits)
(3) Set up the output digital volume (Addr: 1AH and 1BH)
When OVOLC bit is â1â (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Stereo Line-Amp: LOPS3 bit = â0â Ã â1â
(5) Power-up DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = â0â â â1â
LOUT3 and ROUT3 pins rise up to VCOM voltage after PMLO3 and PMRO3 bits are changed to â1â. Rise
time is 300ms(max.) at C=1μF and AVDD=3.3V.
(6) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = â1â Ã â0â
LOPS3 bit should be set to â0â after LOUT3 and ROUT3 pins rise up. Stereo Line-Amp goes to normal
operation by setting LOPS3 bit to â0â.
(7) Enter power-save mode of Stereo Line-Amp: LOPS3 bit: â0â Ã â1â
(8) Power-down DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = â1â â â0â
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(9) Disable the path of âDAC Ã Stereo Line-Ampâ: DACSL = DACSR bits = â1â Ã â0â
(10) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = â1â Ã â0â
LOPS3 bit should be set to â0â after LOUT3 and ROUT3 pins fall down.
MS0666-E-02
- 154 -
2010/06
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