AK4671_10 Datasheet, PDF (26/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

■ Timing Diagram
MCKI
LRCK
BICK
MCKO
1/fCLK
tCLKH
tCLKL
1/fs
VIH1
VIL1
tLRCKH
tLRCKL
tBCK
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCKH
tBCKL
1/fMCK
50%DVDD
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
Note 59. MCKO is not available at EXT Master mode.
[AK4671]
LRCK
tLRCKH
tDBF
50%DVDD
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
SDTO
SDTI
tBSD
tSDS
MSB
tSDH
50%DVDD
50%DVDD
VIH1
VIL1
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0666-E-02
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2010/06