AK4671_10 Datasheet, PDF (159/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ MIC Input Phone Call (Mono)
MIC Control 1
(Addr:04H, D7-0)
MIC Control 2
(Addr:05H, D3-0)
HPFAD bit
(Addr:1DH, D1)
HPF bit
(Addr:1DH, D4)
00H
(1)
0101
0
(2)
0
14H
1010
1
(8)
1
PFMXL1-0 bits
(Addr:15H, D1-0)
EQ bit
(Addr:18H, D3)
IVL7-0 bits
(Addr:12H, D7-0)
PMMP bit
(Addr:00H, D1)
PMMICL bit
PMADL bit
(Addr:00H, D4&D2)
PMSRA bit
(Addr:53H, D0)
ADC Internal
State
00
0
91H
(3)
(4)
(5)
01
1
BFH
0
(9)
1059 / fs
(6)
(7)
Power Down
Initialize Normal State Power Down
Example:
PCM I/F A: Slave Mode
PCM I/F A Format: Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Pre MIC AMP: +15dB
MIC Power: On
Digital Volume Level: +17.25dB
ADC HPF: Enable
5 band EQ: Enable
(1) Addr:04H, Data:14H
Addr:05H, Data: AAH
(2) Addr:1DH, Data:12H
(3) Addr:15H, Data:01H
(4) Addr:18H, Data:0AH
(5) Addr:12H, Data:BFH
(6) Addr:00H, Data:17H
Addr:53H, Data:05H
Phone Call
(7) Addr:00H, Data:01H
Addr:53H, Data:04H
(8) Addr:1DH, Data:00H
(9) Addr:18H, Data:02H
Figure 124. Mono MIC Input Sequence
(Phone Call Tx: IN1+/IN1- → MICL → ADCL → HPF→ IVL → EQ → SRC-A → PCM I/F A → SDTOA)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, MIC, ADC and SRC-A should be
powered-up in consideration of PLLBT lock time.
(1) Set up Signal Select for MIC Input (Addr: 04H) and Gain for MIC-Amp (Addr: 05H)
(2) Enable ADC High Pass Filter: HPFAD bit = “0” Æ “1”
Enable the coefficient of High Pass Filter: HPF bit = “0” Æ “1” (Coefficient of wind-noise reduction filter is set by
Addr = 28H- 2BH.)
This sequence is an example of HPF setting at fs2=8kHz. The coefficient should be set when HPFAD = HPF bits = “0”
or PMADL = PMADR = PMDAL = PMDAR bits = “0”.
(3) Set up the path of “ADC Æ 5-band EQ”: PFMXL1-0 bits = “00” Æ “01”
(4) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(5) Set up input volume (Addr: 12H)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(6) Power Up MIC, ADC and SRC-A: PMMP = PMMICL = PMADL = PMSRA bits = “0” → “1”
The initialization cycle time of ADC is 1059/fs2=132ms@fs2=8kHz.
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin
going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using
the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up
the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog
input pin and the internal input resistance.
(7) Power Down MIC, ADC and SRC-A: PMMP = PMMICL = PMADL = PMSRA bits = “1” → “0”
IVOL gain is not reset when PMADL = PMADR bits = “0”, and then IVOL operation starts from the setting value when
PMADL or PMADR bit is changed to “1”.
(8) Disable ADC High Pass Filter : HPFAD bit = “1” Æ “0”
Disable the coefficient of High Pass Filter: HPF bit = “1” Æ “0”
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
MS0666-E-02
- 159 -
2010/06