AK4671_10 Datasheet, PDF (48/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4671
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
DSP or μP
32fs or 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 41. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4671
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
≥ 32fs
1fs
DSP or μP
BCLK
LRCK
SDTI
SDTO
Figure 42. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
MS0666-E-02
- 48 -
2010/06