AK4671_10 Datasheet, PDF (100/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ System Clock (PCM I/F)
A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin. The
required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input
frequency is selected by PLLBT3-0 bits (Table 76). BCKO2 bit select the output clock frequency of BICKA or BICKB
pin (Table 77). AK4671 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and
B. Whether PCM I/F A or B should be set as slave mode. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and
BICKB pins are Hi-Z. Table 78 indicates the output data of SDTOA and SDTOB pins in case of PMPCM bit = “0” and
during lock time in Table 76, respectively. Table 79 indicates the output clock at master mode during lock time in Table
76.
Mode PLLBT3 PLLBT2 PLLBT1 PLLBT0
Reference Clock
Input Pin
Frequency
R, C at
VCOCBT pin
R
C
0
0
0
0
0
SYNCA
1fs2
6.8k 220n
1
0
0
0
1
BICKA
16fs2 10k 4.7n
2
0
0
1
0
BICKA
32fs2 10k 4.7n
3
0
0
1
1
BICKA
64fs2 10k 4.7n
4
0
1
0
0
SYNCB
1fs2
6.8k 220n
5
0
1
0
1
BICKB
16fs2 10k 4.7n
6
0
1
1
0
BICKB
32fs2 10k 4.7n
7
0
1
1
1
BICKB
64fs2 10k 4.7n
11
1
0
1
1
BICKA
48fs2 10k 4.7n
15
1
1
1
1
BICKB
48fs2 10k 4.7n
Others
N/A
Table 76. PLLBT Reference Clock (N/A: Not available)
Note 65. Mode 1 is available at only FMTA1 bit = “0”.
Note 66. Mode 5 is available at only FMTB1 bit = “0”.
Lock Time
(max)
260ms
40ms
40ms
40ms
260ms
40ms
40ms
40ms
40ms
40ms
(default)
BCKO2 bit
BICKA/BICKB
Output Frequency
0
16fs2
(default)
1
32fs2
Table 77. BICKA/B Output Frequency
Mode
16bit Linear
8bit A-Law
8bit μ-Law
PMPCM bit = “0”
After PMPCM bit = “0” → “1”
& Before SYNCA/SYNCB Input
L
L
L
H
L
H
Table 78. SDTOA, SDTOB pins Output Data
PMPCM bit = “1”
During Locktime
0000H
11010101b
11111111b
Format
Except for I²S
I²S
SYNCA, SYNCB
L
H
BICKA, BICKB
L
L
Table 79. Output Clock during Lock Time
MS0666-E-02
- 100 -
2010/06