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AK4671_10 Datasheet, PDF (160/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP | |||
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[AK4671]
â Receiver-Amp Output
L1VL2-0 bits
(Addr:08H, D2-0)
SRMXR1-0 bits
(Addr:15H, D7-6)
DACR bit
(Addr:0AH, D0)
RCV bit
(Addr:0FH, D5)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
LOPS1 bit
(Addr:0FH, D2)
PMSRB bit
(Addr:53H, D1)
PMDAR bit
(Addr:00H, D7)
PML/RO1 bits
(Addr:0FH, D1-0)
RCP pin
RCN pin
101
(1)
00
100
01
(10)
0
18H
(2)
(3)
(4)
1
28H
0
(9)
(6)
(7)
(11)
(5)
>1 ms
(8)
Normal Output
Example:
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: â8dB
RCV Volume Level: 0dB
5 band EQ: Enable
(1) Addr:08H, Data:B4H
Addr:15H, Data:40H
Addr:0AH, Data:01H
Addr:0FH, Data:20H
(2) Addr:18H, Data:0AH
(3) Addr:1BH, Data:28H
(4) Addr:0FH, Data:24H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:0FH, Data:27H
(6) Addr:0FH, Data:23H
Phone Call
(7) Addr:0FH, Data:27H
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:0FH, Data:24H
(9) Addr:18H, Data:02H
(10) Addr:0AH, Data:00H
(11) Addr:0FH, Data:20H
Figure 125. Receiver-Amp Output Sequence
(Phone Call Rx: SDTIA â PCM I/F A â SRC-B â EQ â DATT â DACR â RCP/RCN)
<Example>
At first, clocks should be supplied according to âClock Set Upâ sequence. Also, SRC-B, DAC and Receiver-Amp
should be powered-up in consideration of PLLBT lock time.
(1) Set up the path of âSDTIA Ã DAC Ã Receiver-Ampâ: SRMXR1-0 bits = â00â Ã â01â, DACR bit = â0â Ã
â1â, RCV bit = â0â Ã â1â
Set up analog volume for Receiver-Amp (Addr: 08H, L1VL2-0 bits)
(2) Enable 5-band Equalizer: EQ bit = â0â Ã â1â (Boost amount is selected by Addr = 50H-52H.)
(3) Set up the output digital volume (Addr: 1BH)
When OVOLC bit is â1â (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Receiver-Amp: LOPS1 bit = â0â Ã â1â
(5) Power-up SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = â0â â â1â
RCN pin rise up to VCOM voltage after PMLO1 and PMRO1 bits are changed to â1â.
(6) Exit power-save mode of Receiver-Amp: LOPS1 bit = â1â Ã â0â
LOPS1 bit should be set to â0â after PCN pin rise up. Receiver-Amp goes to normal operation by setting
LOPS1 bit to â0â.
(7) Enter power-save mode of Receiver-Amp: LOPS1 bit: â0â Ã â1â
(8) Power-down SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = â1â â â0â
Receiver-Amp becomes to power-down mode.
(9) Disable 5-band Equalizer: EQ bit = â1â Ã â0â
(10) Disable the path of âDAC Ã Receiver-Ampâ: DACR bit = â1â Ã â0â
(11) Exit power-save mode of Receiver-Amp: LOPS1 bit = â1â Ã â0â
LOPS1 bit should be set to â0â after Receiver-Amp power-down.
MS0666-E-02
- 160 -
2010/06
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