AK4671_10 Datasheet, PDF (103/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ PCM I/F A & B Format
AK4671 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and 8bit
μ-Law) independently (Table 82 and Table 83).
Mode
0
1
2
3
LAWA1 LAWA0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 82. PCM I/F A Mode (N/A: Not available)
(default)
Mode
0
1
2
3
LAWB1 LAWB0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 83. PCM I/F B Mode (N/A: Not available)
(default)
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (Table
84 and Table 85). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and μ-Law
Mode, the serial data is MSB first. PCM I/F formats can be used in both master and slave modes. SYNCA/B and
BICKA/B are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
0
1
2
3
FMTA1
0
0
1
1
FMTA0
Format
BICKA
0
Short Frame Sync ≥ 16fs2
1
Long Frame Sync ≥ 16fs2
0
MSB justified ≥ 32fs2
1
I²S
≥ 32fs2
Table 84. PCM I/F A Format
Figure
See Table 86
See Table 88
Figure 92
Figure 93
(default)
Mode
0
1
2
3
FMTB1
0
0
1
1
FMTB0
Format
BICKB
0
Short Frame Sync ≥ 16fs2
1
Long Frame Sync ≥ 16fs2
0
MSB justified ≥ 32fs2
1
I²S
≥ 32fs2
Table 85. PCM I/F B Format
Figure
See Table 87
See Table 89
Figure 92
Figure 93
(default)
In modes 2 and 3, the SDTOA/B is clocked out on the falling edge (“↓”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“↑”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits, and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“↑”) of BICKA and the SDTIA is latched on the
falling edge (“↓”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“↓”) of BICKA and the
SDTIA is latched on the rising edge (“↑”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“↑”) of BICKB and the SDTIB is latched on the
falling edge (“↓”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“↓”) of BICKB and the
SDTIB is latched on the rising edge (“↑”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
MS0666-E-02
- 103 -
2010/06