AK4671_10 Datasheet, PDF (19/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
Pulse Width High
tBCKL
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
tBCK
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency 256fs
fCLK
384fs
512fs
fCLK
fCLK
768fs
1024fs
fCLK
fCLK
Pulse Width Low
Pulse Width High
tCLKL
tCLKH
LRCK Input Timing
Frequency 256fs/384fs
fs
512fs/768fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency 256fs
384fs
fCLK
fCLK
512fs
768fs
fCLK
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
min
8
tBCK−60
45
1/(64fs)
130
130
8
tBCK−60
45
-
-
0.4 x tBCK
0.4 x tBCK
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
8
8
8
tBCK−60
45
312.5
130
130
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
8
-
-
-
-
-
typ
max
Units
-
48
kHz
-
1/fs − tBCK ns
-
55
%
-
1/(32fs)
ns
-
-
ns
-
-
ns
-
-
-
1/(32fs)
1/(64fs)
-
-
48
kHz
1/fs − tBCK ns
55
%
-
ns
-
ns
-
ns
-
ns
-
12.288 MHz
-
18.432 MHz
-
13.312 MHz
-
19.968 MHz
-
13.312 MHz
-
-
ns
-
-
ns
-
48
kHz
-
26
kHz
-
13
kHz
-
1/fs − tBCK ns
-
55
%
-
-
ns
-
-
ns
-
-
ns
-
-
-
-
-
-
-
-
tBCK
50
1/(32fs)
1/(64fs)
50
12.288
18.432
13.312
19.968
13.312
-
-
48
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
ns
ns
kHz
ns
%
ns
ns
%
MS0666-E-02
- 19 -
2010/06