AK4671_10 Datasheet, PDF (20/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BICK “↑” (Note 43)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
LRCK “↑” to BICK “↓” (Note 44)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
−70
-
70
ns
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
−70
-
70
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Slave Mode
LRCK “↑” to BICK “↑” (Note 43)
tLRB
0.4 x tBCK
-
-
ns
LRCK “↑” to BICK “↓” (Note 44)
BICK “↑” to LRCK “↑” (Note 43)
tLRB
0.4 x tBCK
-
tBLR
0.4 x tBCK
-
-
ns
-
ns
BICK “↓” to LRCK “↑” (Note 44)
tBLR
0.4 x tBCK
-
-
ns
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
-
-
80
ns
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
-
-
80
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
Audio Interface Timing (Right/Left justified & I²S)
-
ns
Master Mode
BICK “↓” to LRCK Edge (Note 45)
tMBLR
−40
-
40
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
−70
-
70
ns
BICK “↓” to SDTO
tBSD
−70
-
70
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Slave Mode
LRCK Edge to BICK “↑” (Note 45)
tLRB
50
-
-
ns
BICK “↑” to LRCK Edge (Note 45)
tBLR
50
-
-
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
-
80
ns
BICK “↓” to SDTO
tBSD
-
-
80
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Note 43. MSBS, BCKP bits = “00” or “11”.
Note 44. MSBS, BCKP bits = “01” or “10”.
Note 45. BICK rising edge must not occur at the same time as LRCK edge.
MS0666-E-02
- 20 -
2010/06