AK4671_10 Datasheet, PDF (161/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ Mono Line Output
L3VL1-0 bits
(Addr:11H, D7-D6)
SRMXR1-0 bits
(Addr:15H, D7-6)
DACSR bit
(Addr:0EH, D0)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
LOPS3 bit
(Addr:11H, D2)
PMSRB bit
(Addr:53H, D1)
PMDAR bit
(Addr:00H, D7)
PMRO3 bit
(Addr:11H, D1)
ROUT3 pin
10
(1)
00
0
18H
(2)
(3)
(4)
01
01
1
28H
(10)
0
(9)
(6)
(7)
(11)
(5)
>300 ms
Normal Output
(8)
>300 ms
Example:
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
5 band EQ: Enable
(1) Addr:11H, Data:40H
Addr:15H, Data:40H
Addr:0EH, Data:01H
(2) Addr:18H, Data:0AH
(3) Addr:1BH, Data:28H
(4) Addr:11H, Data:44H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:11H, Data:46H
(6) Addr:11H, Data:42H
Playback
(7) Addr:11H, Data:46H
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:11H, Data:44H
(9) Addr:18H, Data:02H
(10) Addr:0EH, Data:00H
(11) Addr:11H, Data:40H
Figure 126. Mono Lineout Sequence
(Speaker Playback: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → ROUT3 → External SPK-Amp)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, SRC-B, DAC and Mono Line-Amp
should be powered-up in consideration of PLLBT lock time.
(1) Set up the path of “SDTIA Æ DAC Æ Mono Line-Amp”: SRMXR1-0 bits = “00” Æ “01”, DACSR bit = “0” Æ “1”
Set up analog volume for Mono Line-Amp (Addr: 11H, L3VL1-0 bits)
(2) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(3) Set up the output digital volume (Addr: 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Mono Line-Amp: LOPS3 bit = “0” Æ “1”
(5) Power-up SRC-B, DAC and Mono Line-Amp: PMSRB = PMDAR = PMRO3 bits = “0” → “1”
ROUT3 pin rise up to VCOM voltage after PMRO3 bit is changed to “1”. Rise time is 300ms(max.) at C=1μF
and AVDD=3.3V.
(6) Exit power-save mode of Mono Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after ROUT3 pin rise up. Mono Line-Amp goes to normal operation by setting
LOPS3 bit to “0”.
(7) Enter power-save mode of Mono Line-Amp: LOPS3 bit: “0” Æ “1”
(8) Power-down SRC-B, DAC and Mono Line-Amp: PMSRB = PMDAR = PMRO3 bits = “1” → “0”
ROUT3 pin fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
(10) Disable the path of “DAC Æ Mono Line-Amp”: DACSR bit = “1” Æ “0”
(11) Exit power-save mode of Mono Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after ROUT3 pin fall down.
MS0666-E-02
- 161 -
2010/06