AK4671_10 Datasheet, PDF (90/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ Headphone Output (LOUT2/ROUT2 pins)
Power supply voltage for the LOUT2/ROUT2 is supplied from the AVDD pin and centered on the 0.5 x AVDD (typ)
voltage. The load resistance is 16Ω (min). HPG3-0 bits control the output volume (Table 70).
When LOM2 bit = “1”, DAC output signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
When LOOPM2 bit = “1”, the MIC-Amp signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
HPG3-0
Attenuation
DH
+6dB
CH
+3dB
BH
0dB
(default)
AH
−3dB
:
:
:
:
2H
−27dB
1H
−30dB
0H
MUTE
Table 70. LOUT2/ROUT2 Output Volume
When the MUTEN bit is “0”, the common voltage of LOUT2/ROUT2 falls and the outputs (LOUT2 and ROUT2 pins)
change to “L” (VSS1). When the MUTEN bit is “1”, the common voltage rises to VCOM voltage. A capacitor between
the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to AVDD voltage
and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0μF, AVDD=3.3V:
Rise/fall time constant: τ = 100ms(typ), 250ms(max)
Time until the common goes to VSS1 when MUTEN bit = “1” Æ “0”: 500ms(max)
When PMLO2, PMRO2, PMLO2S and PMRO2S bits are “0”, the LOUT2/ROUT2 is powered-down, and the outputs
(LOUT2 and ROUT2 pins) go to “L” (VSS1).
PMLO2 bit, PMRO2 bit,
PMLO2S bit, PMRO2S bit
MUTEN bit
LOUT2 pin,
ROUT2 pin
(1) (2)
(3)
(4)
Figure 72. Power-up/Power-down Timing for LOUT2/ROUT2
(1) LOUT2/ROUT2 power-up (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “1”). The outputs are still VSS1.
(2) LOUT2/ROUT2 common voltage rises up (MUTEN bit = “1”).
(3) LOUT2/ROUT2 common voltage falls down (MUTEN bit = “0”).
(4) LOUT2/ROUT2 power-down (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “0”). The outputs are VSS1. If the power
supply is switched off or LOUT2/ROUT2 is powered-down before the common voltage goes to VSS1, some POP
noise occurs.
MS0666-E-02
- 90 -
2010/06