AK4671_10 Datasheet, PDF (117/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
SDA
SCL
S
start condition
P
stop condition
Figure 105. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
Figure 106. Acknowledge on the I²C-Bus
acknowledge
8
9
clock pulse for
acknowledgement
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 107. Bit Transfer on the I²C-Bus
MS0666-E-02
- 117 -
2010/06