AK4671_10 Datasheet, PDF (18/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; C_L=20pF (except SDA pin) or
400pF (SDA pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
MCKO Output Timing
Frequency
fMCK
0.256
-
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
%
LRCK Output Timing
Frequency
fs
8
-
48
kHz
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
tLRCKH
-
Duty
-
tBCK
50
-
ns
-
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
-
1/(32fs)
-
ns
BCKO bit = “1”
tBCK
-
1/(64fs)
-
ns
Duty Cycle
dBCK
-
50
-
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
MCKO Output Timing
Frequency
fMCK
0.256
-
12.288 MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
%
LRCK Input Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
fs
tLRCKH
Duty
8
tBCK−60
45
-
48
kHz
-
1/fs − tBCK ns
-
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
-
1/(32fs)
ns
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
ns
Pulse Width High
tBCKH 0.4 x tBCK
-
-
ns
MS0666-E-02
- 18 -
2010/06