AK4671_10 Datasheet, PDF (152/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ MIC Input Recording (Stereo)
FS3-0 bits
(Addr:01H, D7-4)
0000
(1)
MIC Control
(Addr:05H, D7-0)
55H
(2)
ALC Control 1
(Ad d r:1 6 H )
ALC Control 2
(Ad d r:1 4 H )
ALC Control 3
(Ad d r:1 7 H )
ALC Control 4
(Ad d r:1 8 H )
ALC State
00H
(3)
E1H
(4)
15H
(5)
02H
(6)
ALC Disable
1111
AAH
05H
E1H
01H
03H
ALC Enable
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +15dB
MIC Power: On
ALC setting: Refer to Table 62
ALC: Enable
(1) Addr:01H, Data:F4H
(2) Addr:05H, Data: AAH
(3) Addr:16H, Data:05H
(4) Addr:14H, Data:E1H
02H
(9)
ALC Disable
(5) Addr:17H, Data:01H
(6) Addr:18H, Data:03H
PMMP bit
(Addr:00H, D1)
PMMICL/R bits
PMADL/R bits
(Addr:00H, D5-2)
ADC Internal
State
Power Down
1059 / fs
(7)
(8)
Initialize Normal State Power Down
(7) Addr:00H, Data:3FH
Recording
(8) Addr:00H, Data:01H
(9) Addr:18H, Data:02H
Figure 114. Stereo MIC Input Sequence
(MIC Recording: LIN1/RIN1 → MICL/R → ADCL/R → ALC → Audio I/F → SDTO)
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure
62”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, MIC and ADC should be powered-up in
consideration of PLL lock time after a sampling frequency is changed.
(2) Set up Gain for MIC-Amp (Addr: 05H)
(3) Set up Timer Select for ALC (Addr: 16H)
(4) Set up REF value for ALC (Addr: 14H)
(5) Set up LMTH1-0, RGAIN1-0 and LMAT1-0 bits (Addr: 17H)
(6) Set up ALC bit (Addr: 18H)
(7) Power Up MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “0” → “1”
The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.
After the ALC bit is set to “1” and ADC block is powered-up, the ALC operation starts from IVOL default value (0dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin
going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using
the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up
the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog
input pin and the internal input resistance.
(8) Power Down MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled
because the ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling
frequency is changed, it should be done after the AK4671 goes to the manual mode (ALC bit = “0”) or ADC block is
powered-down (PMADL = PMADR bits = “0”). IVOL gain is not reset when PMADL = PMADR bits = “0”, and then
IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”.
(9) ALC Disable: ALC bit = “1” → “0”
MS0666-E-02
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2010/06