AK4671_10 Datasheet, PDF (120/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ Register Definitions
Addr
00H
Register Name
AD/DA Power Management
R/W
(default)
D7
PMDAR
R/W
0
D6
PMDAL
R/W
0
D5
PMADR
R/W
0
D4
PMADL
R/W
0
D3
PMMICR
R/W
0
D2
PMMICL
R/W
0
D1
PMMP
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
PMMICL: MIC-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch Power Management
0: Power down (default)
1: Power up
PMADL: ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADR: ADC Rch Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0”, all blocks are powered-down. The register values remain unchanged. Power
supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin should be “L”.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
MS0666-E-02
- 120 -
2010/06