AK4671_10 Datasheet, PDF (50/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or
1024fs). The input frequency of MCKI is selected by FS2-0 bits (Table 13).
Mode
0
1
4
5
6
7
Others
FS3 bit
FS2 bit FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
8kHz ∼ 48kHz
(default)
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 14.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs, 384fs
83dB
512fs, 768fs
93dB
1024fs
93dB
Table 14. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
AK4671
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 384fs, 512fs,
768fs or 1024fs
32fs or 64fs
DSP or μP
MCLK
BCLK
1fs
LRCK
SDTI
SDTO
Figure 44. EXT Master Mode
BCKO bit
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
MS0666-E-02
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2010/06